Non-volatile memories are commonly used in several applications when the data stored in the memory device need to be preserved even in absence of power supply. Within the class of non-volatile memories, electrically programmable (and erasable) memories, such as flash memories, have become very popular in applications in which the data to be stored are not immutable (as it might be case of, e.g., a consolidated code for a microprocessor), being instead necessary from time to time to store new data, or to update the data already stored.
Typically, the memory device includes an arrangement of memory cells, disposed for example in rows and columns, so as to form a matrix.
Depending on the way the memory cells in the matrix are interconnected, two classes of flash memories can be identified: those having a so-called NOR architecture, or NOR flash memories, and those having a so-called NAND architecture, shortly referred to as NAND flash memories. Roughly speaking, in a NOR architecture the memory cells of a same matrix column are connected in parallel to a same bit line, whereas in a NAND architecture groups of memory cells of a same matrix column are serially interconnected so as to form respective strings, which strings are then connected in parallel to each other to a same bit line.
Compared to NOR flash memories, NAND flash memories are more compact (a lower number of contacts in the matrix are required), and they are also better suited for applications such as file storage.
In the NAND architecture, the memory space is ideally partitioned into a plurality of memory pages, each page corresponding to a block of memory cells that, in operation, are read or written simultaneously, i.e. in parallel to each other. The number of memory cells in each block determines the size (i.e., the number of bits) of the memory page. Nowadays, memory pages of 8192 cells are rather typical, but larger memory pages are also encountered, for example of 16384 cells.
Clearly, the memory cannot have so high a number of Input/Output (I/O) terminals as to enable transferring in parallel such long data words; usually, eight or sixteen I/O terminals are in fact provided; thus, some kind of “segmentation” of the memory page is necessary for interfacing the memory with the outside world.
To this purpose, a circuit arrangement called a “page buffer” is provided in the memory for managing the operations of reading the information stored in the memory cells of a selected memory page, or writing new information thereinto. In very general terms, the page buffer includes a buffer register of size equal to that of the memory page, wherein data read (in parallel) from the memory cells of a selected page are temporarily stored, before being serially outputted in chunks of, e.g., eight or sixteen bits, depending on the number of I/O terminals of the memory. Similarly, when data are to be written into the memory, the page buffer is replenished with data received serially in such eight- or sixteen-bits chunks, and, when the buffer has eventually been filled, the data are written in parallel into the memory cells of a given, selected memory page.
The page buffer includes a relatively high number of volatile storage elements, typically bistable elements or latches, in a number corresponding to the number of memory cells of the memory page.
The basic operations that usually are performed on the memory cells are a “page read” (an operation involving reading data from a selected memory page), a “page program” (writing data into a selected memory page), and an “erase” operation, wherein the storing of the memory cells is erased.
So-called “multilevel” memory devices are known, in which each memory cell is capable of storing more than one bit of information. More particularly, referring to the case of memory devices capable of storing a pair of bits of information per memory cell, the latter can be programmed in any one of four different programming states, each one associated with a corresponding logic value of the bit pair. Usually, the programming state of a memory cell is defined by the threshold voltage value of a transistor included in the memory cell; in a memory cell adapted to store two bits, the threshold voltage values of the memory cells may assume one of four different values (or ranges of values). A typical choice is to associate the logic values of the stored bit pair to the states according to a binary sequence “11”, “10”, “01”, “00” corresponding to increasing threshold voltage values, with the logic value “11” that is associated to the state having the lowest threshold voltage value (erased state), and the others associated in succession to states having increasing threshold voltage values. Naturally, for writing data into a two-bit memory cell, or for reading data therefrom, it might be necessary to perform up to three read accesses to the memory cells, using different references.
A solution known in the art for reducing the number of read accesses necessary to retrieve the stored data consists of using a different association rule between logic values and states, that make use of the so called “Gray code.” In this way, the logic values are associated to the states according to the binary sequence “11”, “10”, “00”, “01”, with the logic value “11” that is associated to the erased state, and the others that are associated in succession to states having increasing threshold voltage values. The main feature of using the Gray code consists in the fact that “adjacent” programming states (in terms of threshold voltage values) have corresponding logic values that differ from each other by only one bit. This feature implies a series of advantages.
Page buffers using the Gray code that are known in the art are disclosed for example in the U.S. Pat. No. 6,545,909 and in the United States Patent Application 2002/0126531, both of which are hereby incorporated herein by reference.
In view of the state of the art outlined in the foregoing, the Applicant has faced the problem of how to improve the known solution for implementing a page buffer adapted to manage the operations necessary to the functioning of a multi-level NAND flash memory.